Darja Nonaca

Darja Nonaca Silicon Engineer and PhD Candidate at ETH Zurich

I am a PhD student at ETH Zurich in the Integrated Information Processing (IIP) Group led by Prof. Christoph Studer, where I explore techniques to design low-latency and low-power digital hardware accelerators.

In the first years of my PhD, I focused on hardware-software co-design to minimize the processing latency of selected algorithms for wireless communication systems. Later, my priority shifted to exploring low-power design techniques, such as asynchronous logic methods. In 2025, I visited Prof. Rajit Manohar's Asynchronous VLSI (AVLSI) Group at Yale University, who is developing EDA tools to build asynchronous VLSI circuits.
During my PhD, I have led two tapeouts and I am currently working on the third one. In my free time, I model in the anechoic chambers.

My Chips

Mothra

This 22FDX silicon implements a matrix inversion accelerator for Hermitian, positive-definite matrices, a key operation in many wireless communication algorithms such as MIMO detection and precoding. We compute an explicit inverse of a 16×16 matrix using a block-LDL (BLDL) factorization algorithm. Our hardware architecture is composed of a systolic array of programmable processing elements, to i) compute the multiplication of an Hermitian matrix by its transpose (a pre-processing step prior matrix inversion for an LMMSE detector), and to ii) compute the back-substitution step after the BLDL factorization. The block-LDL factorization has a specialized datapath whose operations are controlled in a processor-like fashion by an FSM. Our ASIC achieves a throughput of 1.44 M mat/s and 416 mW at 870 MHz clock frequency at a latency of 0.7 µs. You can read our publication here.

Wormy

This 22FDX silicon implements a Low-Density Parity-Check (LDPC) decoder operating with a custom-designed short-blocklength LDPC code. LDPC codes, together with their dedicated decoders, form a class of error-correction algorithms used to recover data corrupted by noise. Our custom short-blocklength LDPC code outperforms the 5G standard code (of the same length) in terms of BLER/FER. Our decoder can operate with three different rates and has an early termination engine that mutes the internal registers once a valid codeword is found, which enables power savings. To achieve high-throughput, we inserted a second register in the critical path. This technique, known as pipeline interleaving, allows the processing of two independent codewords simultaneously. On this chip, we were able to feed through a 1.45 GHz clock by placing a custom-designed buffer on the die. You can read our publication here.

Projects

Fixed-Point Arithmetic Library for SystemVerilog

We created a collection of synthesizable SystemVerilog modules, each implementing a parametrizable fixed-point arithmetic operation. Each module has a perfectely matching Matlab and Python models for verification purposes. The modules have the following configurable parameters: Integer and fractional length, signess type (signed or unsigned), and quantization mode for the MSB (saturation or wrap-around) and LSB (truncation or round to the nearest for the LSB). Our library was used in Mothra and Wormy chips, which makes it silicon-validated.

Implementation of Asynchronous VLSI Circuits

At the moment I am working on implementing VLSI circuits with asynchronous logic and comparing their power efficiency to synchronous designs. A tapeout is on the way! More about this comparison will be found in my thesis.

Resources

When I started learning about asynchronous logic design, some popular resources were hard to read coming from a synchronous background. There is a lot of new terminology, and the performance metrics are quite different. Hence, I decided to write a small guide to help engineers with a synchronous design background like me to understand better how asynchronous logic works.

This section is under construction and will be updated very soon.

Contact

I am always happy to chat about work! The fastest way to reach me is email at my_name.my_lastname@gmail.com.
Do not hesitate to reach out if you have any question, suggestion, or would like to discuss potential collaborations.